http://halicery.com/Hardware/Live video on S3 chips/S3's Local Peripherial Bus.html

Notes on S3's Local Peripherial Bus (LPB)

The LPB function

The LPB is a dedicated 16-bit hardware data path to connect external devices directly to S3 graphics chips, like video digitizers or hardware MPEG-1 decoders (eg. S3's own Scenic/MX2 or the C-Cube CL480). When interfacing video digitizer chips, LPB clocks in raw YUV data into the frame buffer. LD/VS/HS/LCLK pins are usually connected to the LPB connector on the board:

   LPB                +----------------------------------------+                                      
connector             |                                        |              
              16      |           +----+             +-----+   |           
         -----/-----> | LD[0..15] |    | --------->  | MPC |   | <----------->  DRAM
                      |           |    |             +-----+   |               
         -----------> | HS        |LPB |              |        |            
         -----------> | VS        |    |              |        | 
         -----------> | LCLK      |    |              |        | 
                      |           +----+            Streams    | 
                      |                               |        | 
                      |                               |        | 
                      |                               |        | 
                      |                               |        | 
                      |                               +--> DAC | --------> RGB out
                      |                                        | 
                      |                ViRGE                   | 
                      |             208-pin PQFP               | 
                      |                                        | 
                      |                                        | 
                      |                                        | 
                      +----------------------------------------+                                      

There were quite a few video digitizer chips these times (Bt, Philips, ITT) with output 4:2:2 YCbCr digital video. ITU standardized the format of digital component video signals (see ITU-R BT.656) but with special YCbCr values for sync and other information in the byte stream. Note that ViRGE cannot handle this byte stream, only with HS/VS pins (Bt and ATi Rage can). YUV 4:2:2 uses chroma subsampling 1:2 horizontally and 4 x 8-bit YUV samples per 2 pixels. The LPB can operate both in 8- and 16-bit YCbCr clocking mode (LPB Mode 010 and 001) - as well as the Bt819/829:

+---+---+ +---+---+ +---+---+ 
|   |   | |   |   | |   |   |              _   _   _   _   _   _ 
+---+---+ +---+---+ +---+---+            _| |_| |_| |_| |_| |_| |_ LCLK        8-bit operation
  Y0  Y1    Y2  Y3   ..                  Cb  Y0  Cr  Y1  ---------> 
   Cb0       Cb2
   Cr0       Cr2                           _   _   _   _   _   _       
                                         _| |_| |_| |_| |_| |_| |_ LCLK
                                          Cb  Cr  --------->                  16-bit operation
                                          Y0  Y1  --------->
                                             

The purpose of the LPB input port is to fill up a rectangle with the arriving YUV data in the FB, similar to a BitBlit but LPB as source. The LPB function with CPU source data (LPB Mode 100) can be used for hardware YUV→RGB conversion: for example displaying JPEG images, MPEG video after decoding without the burden of software YUV→RGB conversion on S3 chips.

S3 MMIO LPB registers define the LPB window with starting address, width/height and stride. VS starts this special BitBlit operation, contents of the data pins are copied to FB on rising edge of LCLK. HS starts a new line by adding stride.

                               VS
   LPB Window         +-------------------+   HS                                   
                      |------------------>|   HS
                      |------>            |   HS
                height|                   |   HS
                      |                   |   HS
                      +-------------------+   HS                                   
                             width 
                              
                      ||||||||||||||||||||| 
                              LCLK      

In theory... either HS or width ends the line and VS or height the window. LPB width/height has an important meaning too and the values programmed into these registers are very sensitive, especially to HS timing. Not to mention memory controller FIFO settings for this heavy, concurrent memory access (LPB, SS, refresh, CPU). It took a lots of experminenting to get it work somehow and some details are still unclear. Things didn't go well in the beginnings..

FC & LPB

Like on the pic on the top, the LPB connector is also a Feature Connector.

Combo boards

On a combo board, like my SPEA, Bt819A is connected to Trio64V+ on-board through a 16-bit path.

The LPB connector

It varies greatly from board to board whether LPB pins of LD[0..15], HS, VS and LCLK are connected, partly or not at all to some kind of Feature Connector. On most S3 boards from the 90's we can find a double header connector with variable number of pins.

(see the ASUS 3DP-V375 DX board). I was unable to track down any peripherial that can be connected here.

34-pin LPB connector

The 34-pin double header connector is the 8-bit LPB connector, an extension of the Standard FC. The extension part has pins for 2 general purpose GOP0/1 (from S3 pin 151 and 190), and SDA/SCL for the I2C bus (S3 pin 205 and 206). The video digitizer chips use the 2-wire I2C bus.

ViRGE LPB:

+-----------------------+----------------------------------------------------------------------------+
|GOP1                   |                                           VS          HS                   |
|  |                    |                                            |           |                   |
| 33    31    29    27  | 25    23    21    19    17    15    13    11     9     7     5     3     1 |
|  .     .     .     .  |  .     .     .     .     .     .     .     .     .     .     .     .     . |
|  .     .     .     .  |  .     .     .     .     .     .     .     .     .     .     .     .     . |
| 34    32    30    28  | 26    24    22    20    18    16    14    12    10     8     6     4     2 |
|  |     |     |        |                          |     |     |     |     |     |     |     |     | |
|GOP0 IICDAT IICCLK     |                        LCLK   P7    P6    P5    P4    P3    P2    P1    P0 |
+-----------------------+----------------------------------------------------------------------------+

CD4052B and the I2C bus

I have a few PCI S3 Trio64V+ and ViRGE/DX boards. For some unknown reason to me all of them have either traces for or a mounted CD4052B channel multiplexer. On cheaper boards it's simply missing, some missing but connections made, some higher-end boards have it.

It's used for the I2C bus to switch the SDA/SCL lines between the monitor DDC and the LPB connector (or some on-board I2C device). The CD4052B has 2 selector pin inputs (A and B) to switch signal input to 4 possible outputs (see CD4052B data sheet). GOP0/1 from ViRGE is connected to A/B.

                               LPB
                            connector
                           IICDAT/IICCLK
                                |
      DDC                       |
      VGA                       |
    connector    ---------  CD4052B  -------- ViRGE
    SDA pin12 
    SCL pin15 
   

The original purpose is for VL-bus configuations only, where SDA/SCL pins are multiplexed with BLANK/ESYNC#. On PCI configuations SDA/SCL pins are not multiplexed. So why does it exist on PCI S3 boards? My guess it's for simplicity and board design to use the same blueprints maybe? Or the FC operation. The I2C bus itself does not require any swithing and more devices can simply attach to the 2 wires.

  +----- 4.7KΩ -- Vcc             
  |  +---- 4.7KΩ -- Vcc             
  |  |                           
  +----- 
  |  +-- I2C device
  |  |
  +----- 
  |  +-- ... 
  |  |
  +----- 
  |  +-- I2C device
  |  |
 SCL |
    SDA

The pull-up resistors are also present on all my S3 boards. Some has doubles because of the CD4052B-design and completely useless, especially when CD4052B itself is missing like on this one with 2 x 2 10KΩ pull-up resistors:

On this low-end S3 Trio64V2 board the CD4052B is missing, but traces for I2C and LPB are there:

On this low-end S3 Trio64V+ board there is no CD4052B, and the two I2C bus parts are connected after assembly:


ASUS 3DP-V375

On the ASUS 3DP-V375 DX board there are 2 connectors, one 34-pin for 8-bit and one 50-pin connector for 16-bit interface to attach TV-Tuners, Video Capture cards, Hardware MPEG decoder add-on cards, or other compatible LPB expansion cards.

The ASUS 3DP-V375 DX board f.ex. has a 50-pin connector for 16-bit interface.

                                              +-----------------------+----------------------------------------------------------------------------+
                                              |GOP1                   |                                           VS          HS                   |
  |     |     |     |     |     |     |     | |  |                    |                                            |           |                   |  
 49    47    45    43    41    39    37    35 | 33    31    29    27  | 25    23    21    19    17    15    13    11     9     7     5     3     1 |
  .     .     .     .     .     .     .     . |  .     .     .     .  |  .     .     .     .     .     .     .     .     .     .     .     .     . |
  .     .     .     .     .     .     .     . |  .     .     .     .  |  .     .     .     .     .     .     .     .     .     .     .     .     . |
 50    48    46    44    42    40    38    36 | 34    32    30    28  | 26    24    22    20    18    16    14    12    10     8     6     4     2 |
  |     |     |     |     |     |     |     | |  |     |     |        |                          |     |     |     |     |     |     |     |     | |
                                              |GOP0 IICDAT IICCLK     |                        LCLK   P7    P6    P5    P4    P3    P2    P1    P0 |
                                              +-----------------------+----------------------------------------------------------------------------+

to clock in digital YUV video data and write into the FB through the LPB path. After that the Streams Processor reads out this data, converts to RGB with optional stretching and color keying, blending with the other stream:

This operation is very different from the legacy Feature Connector mode (see here), which uses (almost) the same connector and pins. So the first thing to do is to clear SRD_1 to swith on LPB mode (the S3 BIOS sets up the chip in Feature Connector mode).

Since the Trio64V+ S3 chips' LPB is a dedicated hardware data path that can clock in 8/16-bit raw YUV data into the frame buffer through the Local Peripherial Bus (LPB). Digitizers, like the Bt can output data streams like that, eg. 4:2:2 YCbCr digital video.
Internally, a few registers control the operation of the LPB.

Many S3 boards had a 34-pin dual row header connector for 8-bit YUV data (the 26-pin Standard Feature Connector was extended with an 8-pin part for the I2C bus and 2 GP pins), like on these two boards I have. On the second one the extra 8-pin header is not even soldered (but connected):



Note the missing channel multiplexers on both. Clearly, these boards were of the cheaper ones, not intended to connect external peripherials as digitizers to it like other higher-end S3 boards. Anyway, this didn't stop me trying it..

Obviously, we cannot just connect ATI-TV ISA's 40-pin AMC to the 34-pin LPB connector anyway. By the way, 40- and 34 pin ribbon cables were used for IDE and floppy, so they can be used just make it shorter (for AMC ATI says max. 10").


Mon Feb 11 08:33:44 UTC+0100 2019 © A. Tarpai